Optimization of Column Compression Multipliers

Optimization of Column Compression Multipliers

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With delay proportional to the logarithm of the multiplier word length, column compression multipliers are the fastest multipliers. Unfortunately, since the design community has assumed that fast multiplication can only be realized through custom design and layout, column compression multipliers are often dismissed as too time consuming and complex because of their irregular structure. This research demonstrates that an automated multiplier generation and layout process makes the column compression multiplier a viable option for application specific CMOS products. Techniques for optimal multiplier designs are identified through analysis of area, delay, and power characteristics of Wallace, Dadda, and Reduced Area multipliers.In 2000, Hsiao and Jiang [64] produced a synthesizer which generates gate level Verilog code for a fast column ... alt;8 - 64agt; = number of bits in the multiplicand (M) or multiplier (N) alt;adderagt; = alt;rc | cla | NA agt; = ripple carry, carry lookahead adder, anbsp;...

Title:Optimization of Column Compression Multipliers
Author: K'Andrea Catherine Bickerstaff
Publisher:ProQuest - 2007

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