Digital Design (Verilog)

Digital Design (Verilog)

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Digital Design: An Embedded Systems Approach Using Verilog provides a foundation in digital design for students in computer engineering, electrical engineering and computer science courses. It takes an up-to-date and modern approach of presenting digital logic design as an activity in a larger systems design context. Rather than focus on aspects of digital design that have little relevance in a realistic design context, this book concentrates on modern and evolving knowledge and design skills. Hardware description language (HDL)-based design and verification is emphasized--Verilog examples are used extensively throughout. By treating digital logic as part of embedded systems design, this book provides an understanding of the hardware needed in the analysis and design of systems comprising both hardware and software components. Includes a Web site with links to vendor tools, labs and tutorials. a€c Presents digital logic design as an activity in a larger systems design context. a€c Features extensive use of Verilog examples to demonstrate HDL (hardware description language) usage at the abstract behavioural level and register transfer level, as well as for low-level verification and verification environments. a€c Includes worked examples throughout to enhance the reader's understanding and retention of the material. a€c Companion Web site includes links to tools for FPGA design from Synplicity, Mentor Graphics, and Xilinx, Verilog source code for all the examples in the book, lecture slides, laboratory projects, and solutions to exercises.exercise 3.25 Develop a Verilog testbench model for the adder described in Exercise 3.24. exercise 3.26 Perform the following unsigned binary ... 3.30 The magnitude comparator of Figure 3.12 suffers from similar worst-case delay behavior to that of a ripple-carry adder. ... in Section 3.1.3. exercise 3.36 Develop a Verilog model of a converter that converts from a 4-bit unsigned binary code input to a 4-bitanbsp;...

Title:Digital Design (Verilog)
Author: Peter J. Ashenden
Publisher:Elsevier - 2007-10-24

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