Analysis of IP Based Implementations of Adders and Multipliers in Submicron and Deep Submicron Technologies

Analysis of IP Based Implementations of Adders and Multipliers in Submicron and Deep Submicron Technologies

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Findings and Conclusions. Various architectures of adders and multipliers available with the DesignWare Building Block IP were implemented in different technologies for various bit widths. Adders and multipliers were implemented in unpipelined and two-stage pipelined configurations. These design implementations were analyzed for key parameters of total dynamic power, leakage power, Energy-Delay product, delay and area at various bit widths. Using the results obtained optimal implementations of adders and multipliers for before mentioned key parameters were summarized. These results were consistent for all implemented bit widths in all implemented technologies. Also, the leakage power was seen to contribute a higher percentage to the value of the average power dissipation in deep submicron technologies when compared to submicron technologies.... of a n-bit Ripple Carry Adder ......................................3 1.3: A 4-bit Carry Look- Ahead Adder Implementation using a Carry Look-Ahead Generator (CLG) ............ .............................................4 1.4: A 16-bit Carry Select Adder Implementation with 4 anbsp;...


Title:Analysis of IP Based Implementations of Adders and Multipliers in Submicron and Deep Submicron Technologies
Author: Vijaya Chandra Kurapati
Publisher:ProQuest - 2008
ISBN-13:

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